The escalating requirements for high density and performance associated with ultra large scale integration require responsive changes in electrical interconnect patterns, which is considered one of the most demanding aspects of ultra-large scale integration technology. Demands for ultra-large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.18 micron and under, e.g., about 0.15 micron and under.
Semiconductor devices typically comprise a substrate and elements, such as transistors and/or memory cells, thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. The formation of gate electrodes and interconnection lines is partly accomplished utilizing conventional photolithographic techniques to form a photoresist mask comprising a pattern and transferring the pattern to an underlying layer or composite by etching the exposed underlying regions.
In accordance with conventional practices, an anti-reflective coating (ARC) is typically provided between the photoresist layer and an underlying silicon layer to avoid deleterious reflections from the underlying silicon layer during patterning of the photoresist layer. ARCs are chosen for their optical properties and compatibility with the underlying silicon layer and typically include a silicon oxynitride, silicon-rich silicon nitride or titanium nitride. Conventional deep-ultraviolet (deep-UV) photoresist processing typically involves exposure to deep-UV radiation having a wavelength of about 100 nm to about 300 nm.
As miniaturization proceeds apace with an attendant shrinkage in size of individual semiconductor devices and crowding more devices into any given unit area, problems arise with respect to maintaining the accuracy of the dimensions of various features, notably polycrystalline silicon gate electrodes. During conventional processing, the ARC is deposited on an amorphous silicon (subsequently crystallized during processing) or polycrystalline silicon layer and a photomask formed on the ARC. In forming a conductive feature, e.g., gate electrode, the integrity of the ARC is deteriorated by virtue of various processing steps. For example, during ion implantation, the uniformity of its etchability is alternated. Moreover the integrity of the ARC is deteriorated during stripping of resist with a solvent. As a result, during conventional stripping of the ARC, as with hot phosphoric acid or by dry etching employing CF.sub.4 and O.sub.2 chemistry, the underlying silicon layer is damaged, as by pitting.
Conventional methodology for forming a gate electrode is schematically illustrated in FIGS. 1A and 1B, wherein similar features are denoted by similar reference numerals. Adverting to FIG. 1A, amorphous or polycrystalline silicon gate electrode layer 12 is formed on gate dielectric layer 11 overlying substrate 10, and ARC 13 is formed on gate electrode 12. As a result of previous processing, including ion implantation and stripping of the photoresist mask, the integrity of ARC 13 has been damaged in that it does not exhibit a uniform removal rate and exhibits porosity. Consequently, as shown in FIG. 1B, upon stripping ARC 13 in a conventional manner, as by employing hot phosphoric acid or dry etching, the upper surface 14 of a gate electrode 12 is pitted thereby adversely impacting device performance.
There exists a need for methodology enabling patterning of a conductive feature, such as a silicon gate electrode, with improved accuracy and integrity. There exists a further need for such methodology enabling the formation of gate electrodes without surface pitting.